Generally, a memory is a device storing data and becomes an indispensable device in a computer, etc. Recently, with a rapid progress in the computer technology, high efficient systems having the processing capability of high speed data has been manufactured. In these high efficient systems, it is already known fact that the memory device which predominates in the speed characteristic has come to be keenly required. For high speed memory device, the memory device of GaAs materials of the compound semiconductor has been widely used and the GaAs memory devices are superior to all Si memory devices manufactured up to now in speed characteristics.
However, the GaAs memory device has problems that it is behind the Si semiconductor in processing technology, the high density during manufacturing is difficult because the material itself has a complicated characteristics, namely, the parameter variations of a device and a product is high in price caused by deterioration of its yield.
FIG. 1A shows a circuit diagram of the prior art GaAs SRAM memory cell using construction of a Si SRAM memory cell.
In FIG. 1A, the GaAs SRAM memory cell includes a cell latch which stores complemental data and consists of the symmetrical construction of two enhancement field effect transistors (FETs) J11 and J12 and two depletion FETs J13, and two transmission FETs J15 and J16 for transmitting the complemental data of the cell latch to bit lines BIT and BIT, respectively.
Thus, the cell latch composed of bistable construction has a property that it becomes "1" or "0" which is a stable complemental logic data even if somewhat signal is applied. Also, the transmission FETs J15 and J16 are turned ON in case that corresponding work line is only selected, so that they can write data to the cell latch or read out data from the cell latch.
The memory cell shown in FIG. 1B is same construction as that of FIG. 1A except that the depletion FETs J13 and J14 are replaced with load resistances RL12 and RL13.
However, the above construction of the memory cell has disadvantages that the variation of the device parameters is small, while Si RAM is useful under the well established process condition, if the variation of the device parameters becomes large, the cell operation becomes unstable caused by the small variation of the device parameters, and in case that the memory cell caused by the unstable operation is selected, the data having been stored in broken (for example, the change from the state of "0" to "1" or the change from the state of "1" to "0").
FIG. 1C shows circuit diagram illustrating another prior art memory cell which consists of depletion FETs since the manufacture of the enhancement FET may be impossible technically.
In FIG. 1C, the cell latch of the memory includes load resistance RL13 and RL14, driving depletion FETs J17 and J18, diodes D1, D2, D3, D4, D5, D6, D7 and D8 for regulating bias voltage of the depleation FETs J17 and J18 and resistances R1 and R2. Also, write bit lines WBIT and WBIT for writing data to the cell latch are connected to the cell latch through diodes D9 and D10, respectively and a read bit line RBIT for reading out the data from the cell latch is connected to a driving depletion FET J18 through a diode D11 and a reading FET J19.
The memory cell having above construction is disclosed in U.S. Pat. No. 4,575,821 (issued Mar. 11, 1986).
However, since these construction comprises only depletion FETs, its use is difficult in the advanced technology using enhanced FETs together with depletion FETs, its power consumption is high and the driving of a sense amplifier is difficult.
FIG. 1D shows circuit diagram of still another prior art memory cell composed of depletion FETs.
As shown in FIG. 1D, the cell latch of the memory cell includes load resistances RL15 and RL16, drining depletion FETs J22 and J23, diodes D12 and D13 for regulating bias voltage of the depletion FETs and load resistances R3 and R4. And, bit lines BIT and BIT are connected to the cell latch through FETs J20 and J21 for reading out data from the cell latch.
Thus, the technology which can improve operatin characteristic by excluding the influence of bit lines BIT and BIT from the cell latch is disclosed in U.S. Pat. No. 4,981,807 and Japan, Pat. No. 63-160087.
These memory cell, however, doesn't work well in a writing operation because the cell latch consists of only depletion FETs excluding another FETs.
FIG. 1E shows circuit diagram illustrating still another prior art memory cell.
Referring to FIG. 1E, power source Vss is applied to bit lines BIT and BIT through FETs J24 and J25 respectively connected thereto. Moreover, the cell latch as shown in FIG. 1B is connected to the bit lines BIT and BIT and word line WORD. In this construction, when selecting the work line WORD, i.e., a cell selecting signal is applied to the word line WORD, the cell latch among the rising edge f pulse of the word line WORD must transmit the data to the bit line BIT while maintaining the before selecting data as it is.
However, if the variation of the device parameters becomes large in the slightest degree, the data V(1) and V(2) is changed, thereby breaking the stored data as shown in FIG. 1F.
Thus, in case that the variation of the device parameters is excessive as GaAs memory, the breakdown of the data deteriorates a yield of the memory and makes the manufacturing of high integrated memory difficult.